1. Field of the Invention
The present invention relates to a static random access memory (SRAM), and more particularly to an SRAM cell which can reduce a soft error rate and a method of manufacturing the same.
2. Description of the Prior Art
An SRAM is a memory device which is driven at a high speed, at a low power, and in a simple manner. The SRAM is advantageous in that a periodical refresh of stored information is not required, unlike a dynamic random access memory (DRAM), and also designing is easy.
Such an SRAM comprises a pair of access-devices for cell selection, a pair of pull-down devices functioning as driving devices, a pair of pull-up devices functioning as load devices. Herein, the pull-up devices are classified into three types, that is, a Full CMOS type, a High Load Resistor type, and a Thin Film Transistor type, according to their structure.
FIG. 1 is a circuit diagram of a conventional Full CMOS-type SRAM cell. As shown in FIG. 1, a SRAM cell comprises a cross-coupled pair of inverters, wherein the inverters include a pair of pull-up devices Tp1 and Tp2 each of which is constituted by a PMOS and a pair of pull-down devices Td1 and Td2 each of which is constituted by an NMOS. Access devices Ta1 and Ta2, each of which is constituted by an NMOS and driven selectively according to a signal of a word line WL, are respectively disposed between the drain of a pull-down device Td1 and a bit line BL and between the drain of a pull-down device Td2 and a bit line bar /BL.
In FIG. 1, reference symbol N denotes a node at which an access device Ta1, a pull-up device Tp1, and a pull-down device Tp1 are connected in common, and reference symbol NB denotes a node bar at which an access device Ta2, a pull-up device Tp2, and a pull-down device Td2 are connected in common.
Recently, with the improvement of technology and density of a memory cell and the decrease of the operation voltage, the soft error rate has emerged as a hot issue.
The “soft error rate” refers to the discordance between written information and read information in/from a memory cell, that is, a fault caused by information loss. The soft error rate is a concept different from errors caused by a physical defect, and emerges as random Bit fail in a memory cell.
A cause for such soft error may be alpha (α) particles emitted from radioactive elements, such as uranium, thorium, and americium. That is, when alpha particles pass a storage area of a cell, charge Up-set is generated to cause electric charge stored in a cell node to be lost. As a result, the actual stored information changes, thus causing soft error.
For example, when alpha particles, which have lost half of their total energy in passing through a protection layer of a chip and thus having an energy of about 4 Mev, pass through a storage area, the alpha particles move about 25 μm. At this time, about 106 electron-hole pairs (EHPs) are generated, which are an amount of electric charge sufficient to cause a soft error.
Actually, alpha particles existing in epoxy molding compound (EMC) and so forth collide with silicon nuclei, thus making energetic silicon nuclei, and this energy permits carriers (EHP) connected with silicon nuclei to become free carriers. Among these free carriers, holes are recombined in a p-well and are annihilated, while electrons pass a diffusion and drift area, arrive at a cell node, and then change the electric charge distribution of the cell node. Therefore, node voltage is varied, so that soft error is caused.
Such soft errors have actually emerged as a big problem in SRAM cells, and a number of studies have been made to solve this problem.